MTJs (Magnetic Tunnel Junctions) may be programmed at the intersections of Word Line and Bit Line currents in MRAM cells. The possibility of cells along the same word and bit lines being disturbed is, however, a major concern. A Segmented Word Line approach, as described in “Select Line Architecture for Magnetic Random Access Memories” (US Patent Application Publication: US 2002/0176272 A 1), eliminated disturb conditions for cells on the same word line outside the selected segment. When the operating point is chosen deep along the hard axis, the required bidirectional bit line currents to program the selected cells are significantly reduced. The possibility of a disturb along the bit line is also reduced. This is an ideal MRAM operating condition but the silicon area overhead due to the large size of the segmented word line select transistor makes widespread application impractical.
In FIG. 1, a typical segmented word line array is shown. Since the word line programming current only goes through the selected Segmented Word Line Source, the selected word line segment and the word line segment select a transistor to Ground or a Segmented Word Line Return, any MTJs 11 outside this word line segment being unaffected by this programming current.
In FIG. 2, the composite characteristics of MTJs within an array are shown on an asteroid chart as the shaded areas. With a segmented word line MRAM array, the word line current can be biased deep into the region where only very small bi-directional bit line currents are needed to program the MTJs. As an example, when a Word Line current is biased at point a and the bi-directional bit line currents are biased at points b and c, the margins to ensure programming of all bits within the array are shown as Im and the safety margins for not disturbing any bits along the bit lines are shown as Is.
This mode of word line current biasing requires every bit within the selected word line segment to be programmed in one direction or the other. Otherwise, they will end up in random states. The Word Line bias current required in this condition is high, therefore the size of a Segmented Word Line Select Transistor will be a big overhead compared with the number of cells (or bit lines) within an selected segment.
In a conventional approach, as seen in FIG. 1, each MTJ 11 is isolated by a transistor. This transistor has to be placed directly underneath the MTJ when laying out and constructing the MRAM array. Therefore, the big Segmented Word Line Select Transistor must be placed adjacent to the segment. This transistor and its associated connection area are a big overheads of the segmented word line approach. By using one single isolation transistor for many or all the MTJs within a word line segment, the isolation transistor (or transistors) will not take up all the area beneath the MTJs, leaving room for the Segmented Word Line Select Transistor. However, there are several undesirable effects of using a single isolation transistor for several MTJs.
Since the sensing currents of all MTJs within a word line segment will flow through a single isolation transistor, the voltage on the Common Bottom Electrode node will vary depending on the resistance states (i.e. Data Pattern). The size of the Common Isolation Transistor needs to be large to reduce this effect. Another undesirable effect of using a single isolation transistor is the fairly big voltage difference, depending on bit line resistance and bit line programming current values, between bit lines in a big array during Write due to the bidirectional nature of Bit Line programming currents. This big potential difference between adjacent bit lines within a word line segment can damage MTJs and reduce programming current.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,335,890 (Roehr et al) discloses global and local word lines where the global word lines are isolated from the memory cells, write lines and bit lines orthogonal, and a switch for each word line segment. U.S. Pat. No. 6,490,217 and U.S. patent application 2002/0176272 (DeBrosse et al) show 1 transistor for each MRAM element.
U.S. Pat. No. 6,816,405 and U.S. patent applications 2004/0240265 (Lu et al) shows a local word line associated with each segment where the local word line is connected to a switch at one end and the a global word line at the other end. Local and global bit lines do not seem to be disclosed. U.S. Pat. No. 6,778,429 (Lu et al) also includes current sinks couplable to global word lines. U.S. Pat. No. 6,711,053 (Tang) discloses a switching device (transistor) for each MTJ.
U.S. Patent Application 2004/0190360 (Scheuerlein) shows word line segments connected vertically without segment switching devices. U.S. patent application 2004/0165424 (Tsang) teaches segmented word lines and segmented bit lines.